`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:37:06 11/01/2011
// Design Name:   VGA_Sync
// Module Name:   C:/Users/Tyson/Documents/Verilog Projects/CPU svn proj 3710/trunk/VGASynchTEST.v
// Project Name:  CPU
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VGA_Sync
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module VGASynchTEST;

	// Inputs
	reg clk;
	reg reset;

	// Outputs
	wire vga_v_sync;
	wire vga_h_sync;
	wire [9:0] CounterX;
	wire [8:0] CounterY;
	wire inDisplayArea;

	// Instantiate the Unit Under Test (UUT)
	VGA_Sync uut (
	.reset(reset),
		.clk(clk), 
		.vga_v_sync(vga_v_sync), 
		.vga_h_sync(vga_h_sync), 
		.CounterX(CounterX), 
		.CounterY(CounterY), 
		.inDisplayArea(inDisplayArea)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		reset = 0;
		// Wait 100 ns for global reset to finish
		#100;
		reset = 1;
		#100;
		reset = 0;
        
		// Add stimulus here

	end
	
	always begin
	#5; clk = ~clk;
	
	end
      
endmodule

